Signal corruption can happen at almost any stage of the clock chain. It is impossible to tell if a multi-drop topology (one generator feeds multiple destinations) is any better than a daisy-chain topology, since so much depends on the quality of the driver and receiver electronics, the cable impedance matching, how, exactly, the daisy-chain devices pass the clock through, etc.On the 192, we made sure that there was no measurable degradation of the loop sync clock as it passed through the interfaces. We scrutinized this path and had to make several changes in development until it was just right. The net effect is essentially identical to that of a clock DA. Then, any residual jitter on the that loop sync clock is further attenuated by the local clock generator. The result is that the converters are well "shielded" from outside jitter sources. Even though the 192 will attenuate the jitter from the Nanosyncs, you'd be better off just using the HD internal clock. Its intrinsic jitter is considerably lower.